单项选择题 题1：引入多道程序设计技术的目的是(61)。题2：某节点。(路由器)存放的路由信息如表3-1所示。则该网络使用的路由算法最可能是(62)。节点A根据当前的路由信息计算出的到节点D的路由可能为(63)。将路由信息发送到其他节点所采用的基本算法是(64)。为避免路由信息被重复发送，需要给路由信息包编号。设想每秒钟传送一次路由信息，为确保路由信息包的编号在1年内不重复使用，则编号的最短长度应为(65)位。

单项选择题 IPv6是下一代IP协议。IPv6的基本报头包含(26)B，此外还可以包含多个扩展报头。基本报头中的(27)字段指明了一个特定的源站向一个特定目标站发送的分组序列，各个路由器要对该分组序列进行特殊的资源分配，以满足应用程序的特殊传输需求。一个数据流由(28)命名。在IPv6中，地址被扩充为128bit，并且为IPv4保留了一部分地址空间。按照IPv6的地址表示方法，以下地址中属于IPv4地址的是(29)。(30)是IPv6的测试床，实际上是一个基于IPv4的虚拟网络，用于研究和测试IPv6的标准、实现以及IPv4向IPv6的转变过程。

单项选择题 ATM网络采用(11)多路技术传送信元，典型的数据速率为155.5Mbit/s，这样每秒大约可以传送(12)万个信元。采用短的、固定长度的信元，为使用硬件进行高速数据交换创造了条件。ATM是为B-ISDN定义的传输和交换方式，可以适应各种不同特性的电信业务，CBR(Constant Bit Rate)模拟(13)业务，适用这种业务的ATM适配层是(14)，用于ATM局域网仿真的ATM适配层是(15)。

单项选择题 analysis emphasizes the drawing of pictorial system models to document and validate both existing and/or proposed systems. Ultimately, the system models become the(32)for designing and constructing an improved system. (33)is such a technique. The emphasis in this technique is process-centered. Systems analysts draw a series of process models called(34). (35)is another such technique that integrates data and process concerns into constructs called objects.

单项选择题 In recent years, one of the more popular topics for panel discussions at computer conferences and trade(61)has been the 'RISC versus CISC' debate.RISC processors feature a small number of instructions that each executes in(62)machine cycle. CISC processors use complex instructions that can take several cycles to execute.The RISC versus CISC debate won't be decided by panel discussion; it will be won in the marketplace. And the deciding factor may have little to do with(63)of instructions and registers and more to do with parallelism.Since their conception, RISC processors have been evolving toward micro parallelism, incorporating parallel-processing features(64)the processor, RISC processors feature pipelining, whereby many instructions can be decoded while one instruction executes. RISC processors, however, are moving toward pipelines for each unit of the processor.CISC processors also employ pipelining. They have many integer instructions that execute in one cycle, but the varying execution times of CISC instructions(65)the effectiveness of parallelism.